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| Features * * * * * * * * * * Compatible with the JPEG Baseline Standard as Defined by ISO IS 109 18-1 Highly-integrated, Low-cost Single Chip Solution Up to 40 Mbytes/sec Sustained Compression Rate Maximum Processing Rate of 1.6 million pixels/sec Supports 8-bit Grayscale and YUV 4:2:2 Color Space Input and Output Formats Handles Images of Size up to 1024 x 1024 Pixels Fast DCT/IDCT Processor On-chip User-defined Quantization and Huffman Tables Support for Fast as well as Slow/Inexpensive Memories Provides Direct Interface for Microcontroller/Microprocessor Access Applications The AT76C101 JPEG Processor is optimized for use in the following applications: * Digital Cameras * Color Printers and Plotters * Low-cost Image Compression Systems * Video Editing (3-4 frames/sec at CCIR 720 x 480 Image Resolution) JPEG Image Compression Processor AT76C101 Hardware Resources * * * * * On-chip Video Interface Custom Discrete Cosine Transform and Quantization Processor Variable Length and Huffman Encoder/Decoder Programmable Memory Interface (Supports Slow Memories) Microcontroller/Microprocessor Access Bus Pin Configuration 100-Pin QFP SRDATA15-0 SRADDR14-0 PXWE PXRE PXIN PXOUT STOP_PIXEL SRDRIVE H_SYNC V_SYNC PX_CLK CLK_IN M_ADDR19-0 M_DATA7-0 MEM_CS TEST RESET FRAMEND FREEZE MASTER_CS MASTER_WR MASTER_OE BUSY BST_TEST Rev. 0751A-04/98 1 Description The AT76C101 is an Image Compression/Decompression Processor that performs the JPEG Baseline Algorithm. The system is capable of high quality compression and decompression of continues-tone color or monochrome images. The AT76C101 performs the Discrete Cosine Transform, Quantization, and Entropy Encoding during the compression stage and carries out all inverse operations during the decompression phase. The AT76C101 uses an external SRAM as working memory, which is accessed by an onchip video interface. The AT76C101 is designed to operate with minimum host intervention. A host processor is required to program the chip in the required operating mode, and to extract the JPEG header from the compressed bit stream during the decompression phase. Based on this information, it then initializes the internal registers. Once the chip has been initialized, the AT76C101 operates continuously until it has completed compression/decompression of a image frame. The image compression ratio is controlled by the user supplied quantization tables, which are loaded before the compression/decompression operation. Compression ratios from 1:1 to 50:1 are possible depending on the quality and storage requirements of the application. Figure 1. AT76C101-based Image Compression System RAW_OUT Basic System Configuration An AT76C101-based image compression system is shown in Figure 1. The AT76C101 requires the following external devices: * A microcontroller to program and initialize the chip in the required operating mode. This device is also used to strip the JPEG header during decompression and to provide the AT76C101 with the header information. * An external working memory (SRAM) for handling uncompressed/decompressed images. The size of this memory depends on the size of the image being processed. The formula to assess the memory size is given in the Pixel Interface section of this manual. * An external memory device to store the compressed data stream. This external memory can be either a fast memory or a slow inexpensive memory. The size of this memory depends on the needs of the specific application. YUV INPUT BUFFER OUTPUT BUFFER AT76C101 DATA15-0 ADDR15-0 32K x 16 SRAM RE WE SRDATA15-0 SRADDR14-0 PXWE PXRE PXIN PXOUT STOP_PIXEL SRDRIVE H_SYNC V_SYNC PX_CLK CLK_IN M_ADDR19-0 M_DATA7-0 MEM_CS TEST RESET FRAMEND FREEZE MASTER_CS MASTER_WR MASTER_OE BUSY ADDR19-0 DATA7-0 CS COMPRESSED DATA MEMORY SAMPLING & COLOR CONVERSION RGB IMAGE TO DISPLAY VIDEO INTERFACE LOGIC WR OE 24-BIT RGB Image Source MICROCONTROLLER 2 AT76C101 AT76C101 System Overview Pixel Interface The pixel interface is used to input uncompressed data during the compression mode, or to output decompressed data during the decompression mode. The AT76C101 expects uncompressed image data either in YUV 4:2:2 (for color images), or in grayscale format. During decompression, the AT76C101 generates images in the same format. This interface requires an external buffer as working memory (Figure 2). During compression, the external buffer is used to store the incoming pixels. After 8 scan lines are read in, the AT76C101 performs a raster to 8x8 block conversion of the input data. During the inverse operation, the AT76C101 converts the outgoing pixels into the raster format and stores them in the external buffer. The uncompressed data is synchronized with the PX_CLK signal. This clock runs at twice the pixel rate so that two transfers can occur for each pixel, one to read pixel data from the external SRAM and one to write pixel data to the external SRAM. Two signals synchronize video interface operation, HSync and VSync. These are active low, bi-directional signals and they are controlled from the Master bit of the Mode register of the chip. When Master is high, HSync and VSync are generated and driven by the chip. When Master is low, these two signals are read as inputs by the chip. In Master mode, the registers HPeriod, HSyncWidth, VPeriod, and VSyncWidth are used to generate HSync and VSync. HPeriod contains the total number of pixels per scan line, and Figure 2. Memory Organization 0000h 32K x 16 SRAM HSyncWidth, the width of active HSync in number of pixels. VPeriod and VSyncWidth provide the same type of information for VSync in terms of scan lines, rather than pixels. These registers and others are used to control the video interface of the chip. The other registers are HDelay, HActive, VDelay, and VActive. HDelay contains the number of pixels between falling HSync and the first active pixel of a line. HActive contains the number of active blocks in a line. The size of the working memory depends on the size of the image being processed. The external buffer should be deep enough to store 16 scan lines of data at the highest horizontal resolution. The equations for determining the external buffer size are: * Buffer bus width = 16 bits [For YUV data], 8 bits [For Grayscale data] * Buffer size = 16 x (No. of pixels per line) As an example, a system designed to process images of the maximum size of 1024 x 1024 pixels would have the following external buffer requirements: * Buffer size = 16 x 1024 = 16,384 words Thus, this system would require 16K x 16 working memory to process YUV images (color) and 16K x 8 working memory to process grayscale images. As the minimum size of available SRAM is 32K x 8, the SRAM requirements are as follows: YUV/grayscale images: two 32K x 8 SRAM's to form a 32K x 16 SRAM. DATABANK A AFTER COMPRESSION 2000h NOT USED 4000h DATABANK B AFTER DECOMPRESSION 6000h NOT USED 1024 PIXELS 7FFFh 16 BITS SRAM ORGANIZATION FOR MAXIMUM SCAN LINE SIZE OF 1024 PIXELS. EACH DATABANK STORES 8 SCAN LINES OF THE RAW IMAGE. 8 BITS 8 BITS 5C00h SCAN LINE 8 3FEh YU 3FFh YV U V U Y DATABANK B SCAN LINE 1 4400h SCAN LINE 2 YV 000h 001h YV 002h YU 8 BITS 8 BITS Y V 4000h SCAN LINE YU Y U 3 Host Interface This is a 8-bit interface that allows the AT76C101 to transfer the compressed data to an external memory device. This interfaces also allows an external microcontroller/microprocessor (complexity of AT89C51) to access the internal memory (registers and tables) of the AT76C101. Two types of transfers can be carried out through this interface: the compressed data transfers and the microcontroller data accesses. Compressed Data Mode The host interface can work with a number of external memory devices. It has two programmable registers through which the user can specify up to eight wait states that allows the chip to interface with slow memory devices. Data transfers are 8 bit wide and are carried out through the Data Bus, Address Bus and the control signals MEM_CS, MASTER_OE and MASTER_WR. The AT76C101 is the bus master and controls all transfers to the external memory. Other devices cannot access the memory while the AT76C101 is in the operating mode. The cycle time of the compressed data transfer varies from one to eight CLK cycles. This cycle time is controlled by two registers, the Read_Cnt_Reg which controls the read cycle time, and Write_Cnt_Reg which controls the write cycle time. These registers are programmed by the microcontroller during initialization. The address bus is also initialized from the Mem_Start_Addr register, which holds the start address of the compressed data memory. Microcontroller Access Mode In this mode, the main function of the host interface is to allow external devices, (i.e. microcontroller or a host processor) to access the internal memory of the JPEG chip. Figure 3. Data Control This is required to program the AT76C101 in the desired mode of operation, to load the internal quantization and Huffman tables during initialization, and to read the status of the chip for testing purposes. All transfers to the internal memory and tables of the JPEG codec are 8-bit wide. Data is transferred using the Data Bus, Address Bus, and the control signals MASTER_WR, MASTER_OE, MASTER_CS and BUS_BUSY. All transfers carried out in this mode are controlled by the microcontroller. When the AT76C101 chip is operating in normal mode (i.e. either compression or decompression), it acts as a bus master on the external memory/microcontroller bus. Since the AT76C101 has higher priority over the microcontroller for these bus accesses, the microcontroller has to check the availability of the bus (by checking BUS_BUSY) before it can access it. Once all the internal registers of the AT76C101 are set up and the tables are loaded, the AT76C101 is activated by setting the Start_Reg register. Once the compression/decompression operation starts, the AT76C101 takes control of the bus, and gives it up only after the chip has processed the image.The microcontroller can access the internal memory of the AT76C101 only between frames and not during normal mode of operation. Data Control During compression, the AT76C101 monitors the internal image buffers and sends a stall signal (STOP) to prevent the external video interface logic from generating new pixels, in case the internal buffers are full. During decompression, the AT76C101 controls the transfer rate from the compressed data interface, based on the status of the compressed data FIFO (Figure 3). REGISTER FILE & TEST MODULE QUANTIZATION TABLE PIXEL BUFFER DCT COEFFICIENT BUFFER TEST MASTER_CS MASTER_OE MASTER_WR HUFFMAN ENCODER BIT STUFFER UNIT COMP. DATA FIFO HOST INTERFACE SRDATA [15:0] PIXEL BUFFER DCT/IDCT & QUANTIZATION MODULE HUFFMAN TABLES M_ADDR M_DATA MEM_CS BUS_BUSY ZIGZAG UNIT HUFFMAN DECODER PX_CLK SRADDR [14:0] PXRE PXWE PXIN PXOUT H_SYNC V_SYNC BLANK STOP_PIXEL PIXEL INTERFACE HIGH LEVEL CONTROL RESET END_FRAME FREEZE CLK_IN 4 AT76C101 AT76C101 Compressed Data Memory Management The AT76C101 starts reading/writing data from/to the compressed data memory starting from the address location specified by the Mem_Start_Addr register. Once a frame has been processed, the AT76C101 writes the address of the last compressed data into the Mem_End_Addr register. The microcontroller uses this information to keep track of the memory locations having valid images, and to specify the starting memory address of the next image During decompression, the microcontroller has to do some additional processing of the JPEG data stream. The microcontroller extracts and process the JPEG header information from the compressed data stream. Based on this header information, the microcontroller then initializes the internal registers of the AT76C101 and writes the address of the memory location containing the first compressed image data (not the start of the JPEG header) into the Mem_Start_Addr register. It then follows the above mentioned initialization sequence. Initialization Sequence The active high RESET signal resets all the AT76C101 resources including the register file. Once the AT76C101 has been reset, the microcontroller can program the chip to the desired mode of operation. The microcontroller will also have to load the internal Huffman and Quantization Tables. Once the internal registers and tables have been initialized, the microcontroller can initiate a compression/decompression operation by asserting the Start_Reg register. The AT76C101 de-asserts this signal after the final image block is processed. When the AT76C101 completes the processing of an image, it asserts the FRAMEND signal, writes the address of the last compressed data into the Mem_End_Addr register and waits for a new Start_Reg request. Quantization Table Loading The on-chip quantization tables must be loaded with the required values before the normal operation of the chip. The AT76C101's quantization table is a 256x16 RAM, and can store up to four 64-word quantization tables. The upper half of the RAM area is used to store the compression quantization tables and the lower half to store the decompression tables. The organization of the quantization RAM is shown in Figure 4. The Quantization Tables can be loaded only after the Quant_Table_Load_Enable register has been set. Once loaded, the quantization tables remain valid until the power is switched off or until they are reprogrammed (they are unaffected by RESET). The Quant_Table_Load_Enable register has to be reset after the tables are loaded and before normal operation of the chip can begin. Figure 4. Internal Memory Organization (Quantization and MaxMin Tables) 0000h 0000h 0002h Y ENCODING UV QUANTIZATION VALUE (BITS 7-0) 0001h QUANTIZATION VALUE (BITS 15-8) 16 BITS 0080h QUANTIZATION VALUE 0100h Y DECODING UV 0180h QUANTIZATION TABLE 3000h 3000h 3008h DC-Y 3080h DC-UV 3100h AC-Y 3180h AC-UV MIN_CODE (BITS 7-0) 3001h MIN_CODE (BITS 15-8) 3002h MAX_CODE (BITS 7-0) 3003h MAX_CODE (BITS 15-8) 3004h VAL_PTR 3005h 3006h 3007h NOT USED 8 BITS 16 BITS 16 BITS VAL_PTR MAX_CODE MIN_CODE 40 BITS MAXMIN TABLE 5 Before loading, the quantization tables have to be converted from the JPEG interchange format (JPEG_Q_Table) to the AT76C101 specific format (AT76C101_Q_Table). This format varies, based on the mode of operation of the chip (compression or decompression). The steps to convert to the AT76C101 specific format are given below: * The Quantization Tables are stored in the zigzag form in the JPEG interchange format. Convert these tables to the normal (un-zigzagged) form. * Convert to AT76C101 format using the following algorithm where, M_Factor[i][j] = 16,384, if (i=1 and j=1) 32,768/sqrt(2), if (i=1 and j=2.8) or (i=2.8 and j=1) 32,768 otherwise: for (i = 1..8) begin for (j = 1..8) begin if (mode = COMPRESS) AT76C101_Q_Table[i][j] = (M_Factor[i][j]/ JPEG_Q_Table[i][j]) + 0.5 else if (mode = DECOMPRESS) AT76C101_Q_Table[i][j] = JPEG_Q_Table[i][j] end end The Quantization tables are 16 bits wide and are loaded using the host bus. The host bus accesses the quantization Figure 5. Internal Memory Organization (Huffman Tables) 1000h 1000h 1004h table values in two 8-bit halves, with the lower address corresponding to the lower order byte and the higher address corresponding to the higher order byte (Figure 4). Huffman Table Loading Like the Quantization tables, the AT76C101 Huffman tables are specific to the chip. Before normal operation of the chip, the Huffman tables must be loaded in the AT76C101 specific format into the on-chip RAM. The INT_Table_Load_Enable register has to be set to load the Huffman tables. When the Huffman tables are loaded into the internal RAM, they remain valid until the power is switched off or until they are reprogrammed (they are not affected by RESET). The Huffman_Table_Load_Enable register has to be reset after the tables are loaded and before normal operation of the chip can begin. The AT76C101 can store up to four Huffman tables: 2 Huffman AC tables and 2 Huffman DC tables. The memory organization and address mapping of the Huffman tables are given in Figure 5. The Huffman tables are 28 bits wide and consist of three fields, the size of the Huffman code (stored as 1 less than actual size), the Huffman code and the 8-bit symbol corresponding to the Huffman code. Each Huffman table value is accessed from the host bus in four 8-bit slices, with the lower order 8 bits corresponding to the lowest address (for e.g. 2000H) and the highest 8-bit slice (bit 24 through bit 31) corresponding to the highest address (2003H). 8-BIT SYMBOL 1001h CODE (BITS 3-0) 1002h CODE (BITS 11-4) 1003h Y 0000 CODE (BITS 15-12) SIZE -1 1040h 28 BITS UV 0000 CODE 16 BITS DC HUFFMAN TABLE 2000h 2004h SIZE - 1 4 BITS 8-BIT SYMBOL 8 BITS Y 2400h UV AC HUFFMAN TABLE 6 AT76C101 AT76C101 The Huffman tables have the same format in both the compression and decompression mode, but the arrangement of the codes within the tables varies for the two modes. In the compression mode, the Huffman tables are indexed by the 8-bit symbol corresponding to the code. For example, the luminance AC Huffman table value corresponding to the 8bit symbol value of 17 will be stored in the 17th location of the table, i.e. in the address locations 4068 to 4071. In the decompression mode, the Huffman tables are arranged in consecutive locations in increasing order of Huffman size. All codes of the same Huffman size are then arranged in terms of increasing Huffman code value. Appendix A, annex C of the JPEG International Standard gives the procedure for generating the Huffman codes and sizes from the Huffman table information extracted from the compressed JPEG header. MaxMin Table Loading The Maxmin tables are an extra set of tables which are required only for the decompression operation. Similar to the Huffman tables, these tables can be loaded only after the INT_Table_Load_Enable register has been set, and this register has to be reset before normal operation of the AT76C101 can commence. This table is required to keep track of the maximum and minimum Huffman code values for each Huffman code length. Since there is a maximum of 4 Huffman tables allowed and the longest Huffman code is 16 bits wide, the required maxmin table size is 64 words. The four maxmin tables are arranged in increasing order of size and each word of the maxmin table is 40 bits wide with three fields, a pointer to the position of the minimum code of that Huffman size, the minimum Huffman code and the maximum Huffman code corresponding to that Huffman code size. The maxmin tables are accessed by the host bus in terms of five 8-bit slices with the lowest address corresponding to bit 0-7 of the maxmin table value and the highest address corresponding to bit 32-39 (Figure 4). These tables are generated from the AT76C101 specific decompression mode Huffman tables and the algorithm to develop them is given below: for (i = 1..16) begin maxmin_min_code[i] = -1 maxmin_max_code[i] = -1 end for (i=1..total_num_of_huffman_codes) if (maxmin_min_code[size[i]] == -1) begin maxmin_min_code[size[i]] = code[i] maxmin_val_ptr[size[i]] = i end maxmin_max_code[size[i]] = code[i] 7 Signal Description Figure 6. Symbol CLK GND Vcc PWR MAST_CS TEST BST_TEST FREEZE RESET_ PXWE PXRE PWR SRADD14 SRADD13 SRADD12 SRADD11 NC SRADD10 SRADD9 SRADD8 SRADD7 GND SRADD6 SRADD5 SRADD4 GND SRADD3 SRADD2 SRADD1 SRADD0 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 M_DATA7 M_DATA6 GND M_DATA5 M_DATA4 M_DATA3 M_DATA2 M_DATA1 GND M_DATA0 MAST_WR MAST_OE MEM_CS PWR M_ADD0 M_ADD1 M_ADD2 M_ADD3 M_ADD4 PWR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 M_ADD5 M_ADD6 M_ADD7 M_ADD8 M_ADD9 M_ADD10 GND M_ADD11 M_ADD12 M_ADD13 GND M_ADD14 M_ADD15 M_ADD16 M_ADD17 M_ADD18 PWR M_ADD19 BUSY FRAMEND stop_pixel SRDRIVE PWR PX_CLK HSync VSync Vcc GND PXOUT PXIN 8 AT76C101 PWR 81 SRData15 82 SRData14 83 SRData13 84 PWR 85 SRData12 86 SRData11 87 SRData10 88 SRData9 89 SRData8 90 GND 91 SRData7 92 SRData6 93 SRData5 94 SRData4 95 GND 96 SRData3 97 SRData2 98 SRData1 99 SRData0 100 AT76C101 Table 1. Signal Description Signal BST_TEST CLK FREEZE MAST_CS PX_CLK RESET_ TEST HSync M_ADD[19:0] M_DATA[7:0] MAST_OE MAST_WR SRData[15:0] VSync BUSY FRAMEND MEM_CS PXIN PXOUT PXRE PXWE SRADD[14:0] Type Input Input Input Input Input Input Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Output Output Output Output Output Output Output Output Description BIST test pin (used only for testing), should be grounded. Master Clock. Stall Signal, active high. When this signal is asserted, the chip finishes processing the current block and then remains in that state until freeze is pulled low. Master Chip Select Input. Used by microcontroller to access the JPEG chip. Active low. Video Interface Clock (27 MHz fixed). Global Reset Signal, active high, minimum pulse width is three CLK_IN 40 MHz cycles. Active high - Puts chip in test mode. User has access to all internal memory. Must be tied to gnd for normal operation. Indicates start of a horizontal line of the frame. Memory/Microcontroller Address Bus. Used by JPEG chip to access the compressed data memory, and used by microcontroller to access the JPEG chip. Memory/ Microcontroller Data Bus. Used to transfer compressed data to the external storage unit. Also used by microcontroller to program the JPEG chip. Memory/ Microcontroller Read Select. Active low. Used by microcontroller to read from JPEG chip and used by JPEG chip to read compressed data from memory. Memory/Microcontroller Write Select. Active low. Used by microcontroller to write to JPEG and used by JPEG to write to compressed data memory. Pixel Data Bus for inputting uncompressed data in encoding mode, or for outputting decompressed image data in decoding mode. Indicates the start of a frame. Microcontroller bus busy. Signals whether the JPEG chip (high) or microcontroller (low) controls the bus. End of encoding/decoding operation. FRAMEND is active after chip is reset and it remains active until the Start Register is set by the host. Compressed data memory select. Active low. Used by JPEG to select the external memory device used to store the compressed data stream. Pixel Input Control. It is asserted low when pixels are being input from the active portion of the frame into the strip buffer. Pixel Output Control. It ia active only when the pixels from the active region of the field are being read from the strip buffer. Active low. Controls reading data from external memory. Active low. Controls writing to the external memory. Pixel Address Bus. This bus specifies the address location of the external memory device (strip buffer), from/ to which the pixel data is transferred. Supports external memory of up to 32K locations. Indicates that the AT76C101 is driving the SRDATA Bus. When asserted, all operations in the video interface are stopped. Active when the DCT buffers are full, or when the ext. video logic is not ready. SRDRIVE stop_pixel Output Output 9 Table 2. Register File Description Register HPeriod_Low Address 0F800 R/W R/W Description HPeriod-low byte (bit 0 to 7). For color pictures, in Master mode, HPeriod contains one less than the number of pixels between successive HSYNC pulses. In Slave Mode, it contains the time between the falling edge of one HSYNC pulse and the start of the next HSYNC pulse (in terms of pixels). For grayscale images: set this register to 1 less than half the number of pixels between successive Hsync pulses. HPeriod - high byte (bit 8 to 15). HSyncWidth - low byte. Used only in Master mode. For color images: 1 less than the number of pixels that Hsync has to be held active low. For grayscale images: 1 less than half the number of pixels that Hsync has to be held active low. HSyncWidth - high byte. HDelay - low byte. Delay from falling edge of HSYNC to the first active pixel. HDelay - high byte. HActive - low byte. For color images: size of active horizontal line divided by 8. For grayscale images: size of active horizontal line in pixels divided by 16. HActive - high byte. VPeriod - low byte. Used in Master mode - contains the number of lines in the frame_7. VPeriod - high byte. VSyncWidth - low byte. Used in Master mode - one less than the number of lines that Vsync has to be held active low. VSyncWidth - high byte. VDelay - low byte. VDelay - high byte. VActive - low byte. Number of active vertical lines. VActive - high byte. Bit 0 is used to initiate the compression/decompression pipeline. Determine the device operating mode. The function of each bit is shown below. Bit 0: Encode(0)/Decode(1) operation. Bit 1: Color(0)/Grayscale(1) Image. Bit 2: Video Master(1)/Slave(0) Mode. Rest of bits are reserved and should be set to zero. Various bits of this register enable loading the different tables on chip. Bit 0: When set, enables programming the Quantization Tables. Bit 1: When set, enables loading the Huffman Tables, including the MAXMIN tables. The chip sets this register to 1, if an error occurs while decoding. Decoder_Error_Code - high byte. Decoder_Error_Code - high byte. HPeriod_High HSyncWidth_Low 0F801 0F802 R/W R/W HSyncWidth_High HDelay_Low HDelay_High HActive_Low 0F803 0F804 0F805 0F806 R/W R/W R/W R/W HActive_High VPeriod_Low VPeriod_High VSyncWidth_Low 0F807 0F808 0F809 0F80A R/W R/W R/W R/W VSyncWidth_High VDelay_Low VDelay_High VActive_Low VActive_High Start_Reg Mode 0F80B 0F80C 0F80D 0F80E 0F80F 0F810 0F812 R/W R/W R/W R/W R/W R/W R/W Int_Table_Load_Enable 0F813 R/W Decoder_Error Decoder_Error_Code_Low Decoder_Error_Code_High 0F814 0F815 0F816 R R R 10 AT76C101 AT76C101 Table 2. Register File Description Register FIFO_Status Write_Cnt_Reg Read_Cnt_Reg Mem_Start_Addr_Low Mem_Start_Addr_Med Mem_Start_Addr_High Mem_End_Addr_Low Mem_End_Addr_Med Mem_End_Addr_High Address 0F817 0F818 0F819 0F81A 0F81B 0F81C 0F81D 0F81E 0F81F R/W R R/W R/W R/W R/W R/W R R R Description Shows the status of the internal FIFO. Bit 0 is the FIFO full indicator and bit 1 is the FIFO empty indicator. The number of wait states required during a write to external memory is programmed into this register. The number of wait states required during a read from external memory is programmed into this register. Mem_Start_Addr - low byte. The external memory start address is programmed here. Mem_Start_Adrr - middle byte (bit 16 to 31) Mem_Start_Addr - high byte (bit 32 to 39) Mem_End_Addr - low byte. AT76C101 writes the address of the last byte of the frame written into the external memory. Mem_End_Addr - middle byte (bit 16 to 31). Mem_End_Addr - high byte (bit 32 to 39). Table 3. Internal Memory Addressing Module Quantization Tables (256 x 16 bits) DC Huffman Tables (32 x 28 bits) AC Huffman Tables (512 x 28 bits) Maxmin Tables - For Decoding only (64 x 40 bits) Pixel Buffer (4 buffers of size 128 x 8 bits each) DCT Coefficient Buffer (2 buffers of size 64 x 16 each) Compressed Data FIFO (64 x 8 bits) Address Range 0x00000-0x001FF 0x01000-0x0107F 0x03000-0x031FF 0x04000-0x04200 0x04000-0x04200 0x05000-0x050FF Write Port 0x06000-0x06040 Read Port 0x07000-0x07040 11 Table 4. AC Characteristics Symbol tCSS tAS tAH tDS tDH tWPL tWREC tACC tRPL tRREC tCYC tSWR tSOE Parameter Chip Select Setup Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Write Recovery Time Read Access Time Read Pulse Length Read Recovery Time Compressed Memory Read/Write Cycle Time Compressed Memory Write Set-up Time Compressed Memory Read Set-up Time 120 50 1 0.5 0.5 8 Min 3 3 0 3 0 75 125 120 Max Units ns ns ns ns ns ns ns ns ns ns CLK_IN Cycles Figure 7. Compressed Memory Write ADDRESS ADDRESS VALID Figure 9. Microcontroller Write M_ADDR ADDRESS VALID VALID M_DATA DATA VALID tAS tAH tDS tDH tWREC DATA DATA VALID MASTER_WR MEMCS MASTER_CS tCSS tWPL MAST_WR tSWR tCYC Figure 8. Compressed Memory Read ADDRESS ADDRESS VALID Figure 10. Microcontroller Read M_ADDR ADDRESS VALID M_DATA DATA VALID tAS tAH tACC tRREC DATA DATA INVALID DATA VALID MASTER_OE MEMCS MASTER_CS tCSS tRPL MAST_OE tSOE tCYC 12 AT76C101 AT76C101 Electrical Specifications Table 5. Absolute Maximum Ratings Symbol Vcc Vi Vo +-IIk +-IOK IolMAX IohMAX tSH TA TSG Parameter DC supply voltage DC input voltage DC output voltage DC input diode current DC output diode current Continuous output current Continuous output current Time of outputs shorted Temperature range Storage Temperature -40 -65 Min -0.3 -0.3 Max 4.6 Vdd + 0.3V Vdd + 0.3V 10 10 10 10 5 +85 +150 Unit V V V mA mA mA mA sec C C Industrial Conditions Core and standard IOS or see +-IIk or see +-IOk Vi<-0.5V Vi>Vdd+0.5V V0<-0.5V V0>Vdd+0.5V Industrial Industrial Table 6. Recommended Operating Conditions Symbol Vcc Vi V0 TA TR TF Parameter DC supply voltage DC input voltage DC output voltage Temperature range Input rise time Input fall time Min 3 0 0 -40 Typ 3.3 Max 3.6 Vdd Vdd +85 15 15 Unit V V V C ns ns Industrial 10%-90% CMOS 10%-90% CMOS Conditions Table 7. DC Characteristics Symbol Iih Iil Ioz Vil Vih VOL VOH CIN Parameter Input leakage, no pullup Input leakage, no pullup High-impedance output current bi-directional pins Low level input voltage High level input voltage Low level input voltage High level input voltage Input capacitance Min Max Unit A A A V V V V pF Conditions Vin = Vcc = 5.5V Vin = 0, Vcc = 5.5V Vcc = 5.5V CMOS inputs and bi-dir. CMOS inputs and bi-dir. IOL = 5.0mA IOH = 5.0mA 13 |
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